1. Field of the Invention
Embodiments of the present invention generally relate to methods for forming semiconductor devices. More particularly, embodiments of the present invention generally relate to methods for etching a dielectric barrier layer without damaging underlying conductive structures for manufacturing semiconductor devices.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structures on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask, such as a photoresist layer or a hard mask layer, is commonly used to etch structures, such as gate structures, shallow trench isolation (STI), bit lines and the like, or back end dual damascene structures on a substrate. The patterned mask is conventionally fabricated by using a lithographic process to optically transfer a pattern having the desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove undesired portions of the photoresist, thereby creating openings in the remaining photoresist.
As the dimensions of the integrated circuit components are reduced (e.g., to sub-micron dimensions), the materials used to fabricate such components must be carefully selected in order to obtain satisfactory levels of electrical performance. For example, when the distance between adjacent metal interconnects and/or the thickness of the dielectric bulk insulating material that isolates interconnects have sub-micron dimensions, the potential for capacitive coupling between the metal interconnects is high. Capacitive coupling between adjacent metal interconnects may cause cross talk and/or resistance-capacitance (RC) delay which degrades the overall performance of the integrated circuit and may render the circuit inoperable. In order to minimize capacitive coupling between adjacent metal interconnects, low dielectric constant bulk insulating materials (e.g., dielectric constants less than about 4.0) are needed. Examples of low dielectric constant bulk insulating materials include silicon dioxide (SiO2), silicate glass, fluorosilicate glass (FSG), and carbon doped silicon oxide (SiOC), among others.
In addition, a dielectric barrier layer is often utilized to separate the metal interconnects from the dielectric bulk insulating materials. The dielectric barrier layer minimizes the diffusion of the metal from the interconnect material into the dielectric bulk insulating material. Diffusion of the metal into the dielectric bulk insulating material is undesirable because such diffusion can affect the electrical performance of the integrated circuit, or render the circuit inoperative. The dielectric barrier layer needs to have a low dielectric constant in order to maintain the low-k characteristic of the dielectric stack between conductive lines. The dielectric barrier layer also acts as an etch-stop layer for a dielectric bulk insulating layer etching process, so that the underlying metal will not be exposed to the etching environment. The dielectric barrier layer typically has a dielectric constant of about 5.5 or less. Examples of dielectric barrier layer are materials silicon carbide (SiC) and nitrogen containing silicon carbide (SiCN), among others.
After the dielectric barrier layer etching process, the underlying upper surface of the conductive layer is exposed to air. However, early exposure of the underlying conductive layer may result in the conductive layer being subjected to oxidizing conditions during a subsequent etching process or excess exposure to the ambient environment, which may adversely accumulate native oxides or contaminants on the metal surface prior to a subsequent metallization process. Excess native oxide accumulation or contaminants may adversely affect the nucleation capability of the metal elements to adhere to the substrate surface during the metallization process. Furthermore, poor adhesion at the interface may also result in undesired high contact resistance, thereby resulting in undesirably poor electrical properties of the device. In addition, poor nucleation of the metal elements in the back end interconnection may impact not only the electrical performance of the devices, but also on the integration of the conductive contact material subsequently formed thereon.
Thus, there is a need for improved methods to eliminate early exposure of a conductive layer in a dual damascene structure and to etch a dielectric barrier layer with good interface quality control with minimum substrate oxidation and contamination.